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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16364
160-BIT HIGH-VOLTAGE CMOS DRIVER
DESCRIPTION
The PD16364 is a high-voltage CMOS driver for EL display. It consists of 4 x 40/8 x 20-bit data latch, 160-bits data latch, 160-bit level shifter, and a high-voltage CMOS driver. The logic circuit operates on 5-V power supply (CMOS level input), so that it can be connected to a micro-controller. The driver block is comprised of 60 V, 25 mA MAX. high-voltage output buffer, and both the logic block and driver block employ a CMOS, allowing operation with low power consumption.
FEATURES
* High-voltage Full CMOS process * High-voltage output (60 V, 25 mA MAX.) * 4 x 40/8 x 20-bit data latch (4/8-bit data input) * High-speed data transfer (fCLK = 16 MHz: in cascade connection) * Wide operating temperature range (TA = -40 to +85C)
ORDERING INFORMATION
Part Number Package TCP (TAB package)
PD16364N -xxx
Remark The TCP's external shape is customized. To order the required shape, please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S14000EJ2V0DS00 (2nd edition) Date Published November 2002 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
1999
PD16364
1. BLOCK DIAGRAM
DST SCK EIO1 EIO2
Control Circuit
BS
L,/R
20/40-bit Latch Selector 20/40 D0 4 X 20/8 X 20-bit Data Latch 4/8 160 160-bit Data Latch 160 160-bit Level Shifter 160 VDD2 OC 160-bit HIgh-Voltage CMOS Driver VSS2 Data MPX D7 REV VDD1 VSS1
OUT1 OUT2 OUT3 OUT4
OUT OUTOUT OUT 157 158 159 160
Remark /xxx indicates active low signal.
2
Data Sheet S14000EJ2V0DS
PD16364
2. PIN CONFIGURATION (PD16364N-xxx: Copper foil surface, Face-up)
DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY OUT1 OUT2 OUT3 OUT4 OUT5
VSS2 VDD2 VDD2 VSS2
BS L,/R OC REV DST CLK
VSS1
EIO1 EIO2 Copper foil suface
VDD1
D7 D6 D5 D4 D3 D2 D1 D0 OUT156 OUT157 OUT158 OUT159 OUT160 DUMMY DUMMY DUMMY DUMMY DUMMY
VSS2 VDD2 VDD2 VSS2
DUMMY
Remark This figure does not specify the TCP package. Caution Be sure to use all the VDD1, VDD2, VSS1, and VSS2 pins. Keep the VSS1 and VSS2 pins at the same voltage level.
Data Sheet S14000EJ2V0DS
3
PD16364
3. PIN FUNCTIONS
Pin Symbol Pin Name Enable I/O1 I/O I/O L,/R pin = "L" level: Input L,/R pin = "H" level: Output Description
! !
EIO1
EIO2
Enable I/O2
I/O
L,/R pin = "H" level: Input L,/R pin = "L" level: Output
SCK DST
Shift Clock Input Data Strobe Input
Input Input
Fall edge operation. Input shift clock for 4 x 40/8 x 20-bit data latch. Fall edge operation. Data are latched to 160-bits data latch and also set outputs of OUT1 to OUT160.
D0 to D7
Data Input
Input
Data input. When BS is low level, D4 to D7 pins should be connected to VSS1 or VDD1.
L,/R
Select Left or Right Shift
Input
Refer to 4.TRUTH TABLE
OC
Output Control
Input
When OC pin is low level, output is normal operation. When OC pin is high level, output become low level.
REV
Invert Input Data
Input
When REV pin is low level, input data D0 to D7 are latched without inversion. When REV pin is high level, input data D0 to D7 are inverted before latching.
BS
Bus Select
Input
When BS pin is low level, data bus is4 bits. When BS pin is high level, data bus is 8 bits.
OUT1 to OUT160 VDD1 VDD2 VSS1 VSS2
High-voltage output
Output
Output level is VSS2 or VDD2. These outputs are changed by falling edge of DST pin.
Logic power supply Driver power supply Logic ground Driver ground
- - - -
Logic power supply Driver power supply Grounding Grounding
4
Data Sheet S14000EJ2V0DS
PD16364
4. TRUTH TABLE
Shift Register Block (4 x 40 data latch, BS = L)
L,/R L level SCK D3 D2 D1 D0 H level D3 D2 D1 D0 1 1 2 3 4 160 159 158 157 2 5 6 7 8 156 155 154 153 3 9 10 11 12 152 151 150 149 ... ... ... ... ... ... ... ... ... 40 157 158 159 160 4 3 2 1
Shift Register Block (8 x 20 data latch, BS = H) !
L,/R L level SCK D7 D6 D5 D4 D3 D2 D1 D0 H level D7 D6 D5 D4 D3 D2 D1 D0 1 1 2 3 4 5 6 7 8 160 159 158 157 156 155 154 153 2 9 10 11 12 13 14 15 16 152 151 150 149 148 147 146 145 3 17 18 19 20 21 22 23 24 144 143 142 141 140 139 138 137 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 20 153 154 155 156 157 158 159 160 8 7 6 5 4 3 2 1
Control Block
L,/R H level L level EIO1 Out In EIO2 In Out
Driver Block
OC L L L L H REV L L H H x Dn L H L H x L H H L L (All driver outputs are L.) Driver Output
Data Sheet S14000EJ2V0DS
5
PD16364
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS1 = VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage Logic Part Input Voltage Logic Part Output Voltage Driver Part Output Voltage Logic Part Output Current Driver Part Output Current Operating Ambient Temperature Storage Temperature Symbol VDD1 VDD2 VI1 VO1 VO2 IO1 IO2 TA Tstg Rating -0.5 to +6.0 -0.5 to +60 -0.5 to VDD1 + 0.5 -0.5 to VDD1 + 0.5 -0.5 to VDD2 + 0.5 10 25 -40 to +85 -55 to +125 Unit V V V V V mA mA C C
Cautions 1. TA 25C , load should be alleviated at a rate of -4.5 mW/C. 2. Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = -40 to +85C, VSS1 = VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage High-Level Input Voltage Low-Level Input Voltage Driver Part Output Current Symbol VDD1 VDD2 VIH VIL IOL2 IOH2 Conditions MIN. 4.5 20 0.8 VDD1 0 TYP. 5.0 MAX. 5.5 55 VDD1 0.2 VDD1 +20 -20 Unit V V V V mA mA
Caution Turn of and off power sequence must be as follows: Turn-on sequence: VDD1 Input VDD2 Turn-off sequence: VDD2 Input VDD1
6
Data Sheet S14000EJ2V0DS
PD16364
Electrical Characteristics (TA = -40 to +85C, VDD1 = 4.5 to 5.5 V, VDD2 = 55 V, VSS1 = VSS2 = 0 V,)
Parameter High-Level Output Voltage Symbol VOH1 VOH2 Low-Level Output Voltage VOL1 VOL2 High-Level Input Current Low-Level Input Current High-Level Input Voltage Low-Level Input Voltage RON Variance IIH IIL VIH VIL RVAR Conditions Logic, IOH1 = -0.4 mA, OUT1 to OUT160, IOH2 = -1.0 mA Logic, IOL1 = 0.4 mA OUT1 to OUT160, IOL2 = 1.0 mA VI = VDD1 VI = 0 V Logic Logic OUT1 to OUT160 (in one chip under constant Tj Logic Part Dynamic Current Consumption Driver Part Dynamic Current Consumption Standby Current Istandby Note3 500 IDD2 Note2 10 mA IDD1 Note2
Note1
MIN. VDD1 - 0.4 VDD2 - 0.4
TYP.
MAX.
Unit V V
0.4 0.4 5.0 -5.0 0.8 VDD1 0.2 VDD1 30
V V
A A
V V %
) 10 mA
A
Notes 1. Rvar = (1 - Xn/Xavg) x 100 Xn = Impedance of OUTn, Xavg = Impedance of average IOH2 = -1.0 mA, IOL2 = 1.0 mA 2. fSCK = 16 MHz, fDST = 36 kHz, VIN = VDD1 or VSS1, no load 3. VIN = VDD1 or VSS1, no load
Switching Characteristics (TA = -40 to +85C, VDD1 = 4.5 to 5.5 V, VDD2 = 55 V, VSS1 = VSS2 = 0 V)
Parameter Enable Pulse Delay Time Symbol tPLH1 tPHL2 Driver Output Delay Time tPHL3 tPLH3 Input Capacitance CI Conditions DST EIOn, CL = 30 pF Last SCK EIOn, CL = 30 pF DST OUT1 to OUT160, CL = 2000 pF MIN. TYP. MAX. 70 40 7 7 20 Unit ns ns
s s
pF
Data Sheet S14000EJ2V0DS
7
PD16364
Timing Requirement (TA = -40 to +85C, VDD1 = 4.5 to 5.5 V, VDD2 = 55 V, VSS1 = VSS2 = 0 V, tr = tf = 13.0 ns)
Parameter SCK Cycle Time SCK Pulse Width DST Cycle Time DST High-Level Pulse Width DST-SCK Time SCK-DST Time Data Setup Time Data Hold Time REV Setup Time REV Hold Time EIO-SCK Time1 EIO-SCK Time2 Symbol tCSCK PWCLK tCDST PWDST tDST-SCK tSCK-DST tSETUP tHOLD tRSETUP tRHOLD tEIO-SCK1 tEIO-SCK2 EIOn 1st SCK EIOn 1st SCK DST 1st SCK Last SCK DST Conditions MIN. 62 20 1000 30 100 30 20 20 40 30 22 25 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
8
Data Sheet S14000EJ2V0DS
PD16364
Switching Characteristics and Timing Requirements Waveform Timing requirement waveform
0.8 VDD1
Input
0.2 VDD1
0.8 VDD1 or 0.8 VDD2
Output
0.2 VDD1 or 0.2 VDD2
Switching characteristics waveform
tCSCK
PW CLK
PW CLK
tr
tf
LAST
SCK
tSCK-DST
PWDST
tr
tf tDST-SCK
tCDST
DST
tRHOLD tRSETUP
REV
tHOLD tSETUP
D0 to D7
tPHL3,, tPLH3
OUT (n)
SCK
tDST-SCK
1
2
40/20
1
DST
tPLH1
tPHL2
EIO (Output)
tEIO-SCK2 tEIO-SCK1
EIO (Input)
Data Sheet S14000EJ2V0DS
9
10
2 20 1 20 1 20 1 20 2 3 2 2 3 3 3 1 2 IC2 data reading IC3 data reading IC12 data reading
1
SCK
D0 to D7
DST
Timing Example (640 dots x 3/line, BS = H, L,/R = H)
IC1 EIO2
IC1 data reading
Data Sheet S14000EJ2V0DS
IC1 EIO1 / IC1 EIO2
IC2 EIO1 / IC3 EIO2
IC11 EIO1 / IC12 EIO2
OUT1OUT160
PD16364
PD16364
6. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for soldering conditions of the PD16364. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions.
PD16364N-xxx: TCP (TAB package)
Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350C: heating for 2 to 3 seconds: pressure 100g (per solder) Temporary bonding 70 to 100C: pressure 3 to 8 kg/cm2: time 3 to 5 seconds. Real bonding 165 to 180C: pressure 25 to 45 kg/cm2: time 30 to 40 seconds. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.)
ACF (Adhesive Conductive Film)
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time.
Data Sheet S14000EJ2V0DS
11
PD16364
[MEMO]
12
Data Sheet S14000EJ2V0DS
PD16364
[MEMO]
Data Sheet S14000EJ2V0DS
13
PD16364
[MEMO]
14
Data Sheet S14000EJ2V0DS
PD16364
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S14000EJ2V0DS
15
PD16364
Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Semiconductor Device Mounting Technology (C10535E)
* The information in this document is current as of November, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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